1. Field of the Invention
The present invention is related to verification circuitry and a system for monitoring either memory or logic output to determine if the memory or logic is responding to an operation request that ordinarily takes a fixed, predetermined amount of time. More particularly, all of the banks of logic and memory are monitored continuously during the operation of any one of the banks to determine if each of the banks is performing the operation which it is instructed to perform.
2. Description of the Prior Art
Modern high speed computing systems employ a large amount of active high speed memory which is usually in the form of a main storage unit comprising very large scale integrated circuits (VLSI) devices. The many memory devices are mounted on cards or boards to form memory cards which are divided into banks or slices or sections. The access time for reading data out of large solid state memories is kept as small as possible to enhance the speed of the computing system. Thus, many large high speed memories do not employ verification and checking circuits which would degrade the access time of the memory or the logic.
Heretofore, several schemes have been employed to verify that the word being accessed from a memory is the word located at the address being accessed. One such verification system checks the address of the memory word with check bits stored with the memory word.
Another system for checking the data and address of a word being accessed in memory is to access the same data in memory twice and compare the data word accessed from memory, however, a system of this type requires approximately twice the access time as a real time verification system.
The more common system for checking data being accessed from a memory is to perform a parity check on the data and/or a parity check on the data and the address being employed to access the memory, however, this system does not verify that the operation being performed on the data is in fact the desired operation intended to be performed.
Heretofore, verification systems and checking circuits for high speed main frame computers were not employed to verify that cards of memory and plural banks of memory on cards were each performing operations or not performing operations designated under control of a requestor during the time designated for performing the operations requested. There is an unmet need for a verification system for verifying the activity of banks of memory or logic in a computing system.